The invention relates to processing information architecture on an integrated circuit, particularly processing system scheduling and function decoupling architecture for system-on-a-chip (SoC).
The ability to reduce the physical size of the various ICs has led to more combinations of functions on a single chip. Thus, wherein functions previously provided as a combination of several integrated circuits, delineated by functional and physical boundaries such as that provided of a microprocessor chip, a memory controller chip, and a memory chip, are now converging onto a single chip solution (also referred to as a system-on-a-chip (SoC)).
To facilitate the combination of different functions on a single chip, common methods of communication architectures are used. Most SoC functions are currently coupled together using on-chip busses. On-chip busses are standardized bus structures provided as the expected common interface for each functional on-chip component. These busses have several drawbacks limiting the efficiency of the overall design for the following reasons such as: 1) providing only one communication path to be established at any one time causing bus contention; 2) requiring use of standard read and write protocols and bus arbitration to establish system communication, without a scheduling technique for directing communication traffic thereby resulting in overheads and latency to gain bus accesses and arbitrate the busses.
Many of the components integrated on a chip today are modeled on their discrete counterparts, and not integrated as a single chip. Thus, they are inherently unable to exploit the SoC environment. The resulting architecture is neither scalable nor can it be easily optimized for a particular application. Accordingly, it is desirable to have a high performance, homogenous, scalable method and system for managing communication within an SoC architecture that allows a variety of different functions to be brought together and their full synergistic performance realized by decoupling the functions (isolated from other functions within the chip), and providing an efficient system scheduling for data flow around the chip.
A high performance method and system for processing information on an integrated circuit, also referred herein as a SoC processing method and system, is provided by decoupling the various on-chip functions, such as memory, I/O interface, multi-media applications co-processors, etc., while also providing communication means between these functions.
The high performance SoC processing method and system comprises decoupling a microprocessor core into discrete functional components such as, for example, a segregated centralized debug unit, a floating-point vector processor, and an integer vector processor. Each discrete functional component, also referred herein as intellectual property (IP) engines, is individually isolated from each other functional processing IP engine to allow functional component performance optimization within the SoC processing system. A limbic processor is also provided that comprises a common system scheduler to coordinate the data flow around the SoC processing system. Each isolated SoC function can then operate at higher performance and frequencies, independent of the system clock speeds.